1. Field of the Invention
The present invention relates generally to a digital clock modulator and more particularly to an adaptable clock control method and apparatus for a direct access storage device (DASD).
2. Description of the Prior Art
Computers often include auxiliary memory storage units having media on which data can be written and from which data can be read for later use. Disk drive units incorporating stacked, commonly rotated rigid magnetic disks are used for storage of data in magnetic form on the disk surfaces. Data is recorded in concentric, radially spaced data information tracks arrayed on the surfaces of the disks. Transducer heads driven in a path toward and away from the drive axis write data to the disks and read data from the disks.
All DASD units must have a method to position each data head over the proper radial location to write a track and again, to position it very close to the same location to read the track. With the higher level files using a voice coil type of actuator, a feedback mechanism must be provided to locate and stably hold the head on a given track. Typically, track accessing and track following is provided utilizing a magnetically written pattern in the DASD unit. A dedicated servo system employs one surface of one of the disks in the DASD on which to have all the tracking and access information. A sector servo system uses small portions of tracks between each or between several sectors on each track of each data surface to provide the tracking and access information. A hybrid servo system uses both to obtain advantages of each type of servo. Examples of known positioning and servo systems are provided by U.S. patents U.S. Pat. Nos. 4,133,011 to Kurzweil, Jr.; 4,297,734 to Laishley et al.; 4,297,737 to Andersen et al.; 4,488,189 to Axmear et al.; and 4,575,776 to Stephens et al.
Achievement of high data density and high data rates has resulted in the use of a partial-response maximum-likelihood (PRML) channel for writing and reading digital data on the disks.
As a result, a problem exists to interface a high speed clock used with the PRML channel with the symmetry and frequency limited conventional disk controller. Both the timing problem of interfacing the chips and the variation allowed by the motor controlling the rotational speed of the disks has required implementation of expensive analog clock generation circuits or changing the architecture of the disk controller chip for supplying the necessary clock structure while keeping synchronized to the RPM of the disk during reads.